Telephone Circuit Conditioning

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Telephone Circuit Conditioning - SS033400001
Validation Information
Contents - SS033400003
Skill Level 1
Introduction - SS033400005
Contents - SS033400006
Lesson 1. Noise and Interference Measurements
Idle Circuit Noise Test.
Recording of test data. - SS033400009
Figure 1-2. Idle circuit noise data sheet, sample.
Impulse Noise Test.
Figure 1-3. Impulse noise test, block diagram.
Figure 1-4. Impulse noise data sheet, sample.
Performing the test. - SS033400014
Test arrangement. - SS033400015
Performing the test. - SS033400016
Figure 1-6. Harmonic distortion data sheet, sample.
Intermodulation Distortion.
Single-Tone Interference.
Figure 1-7. Single-tone interference test, block diagram.
Performing the test. - SS033400021
Figure 1-8. Single-tone interference data sheet, sample.
Figure 1-9. C-message weighting curve.
Maximum Change in Audio Frequency.
Recording of test data. - SS033400025
Figure 1-11. Maximum change in audio-frequency data sheet, sample.
Terminal Impedance.
Test arrangement.
Figure 1-12. Terminal impedance tests, block diagram.
Performing the tests. - SS033400030
Figure 1-13. Terminal impedance data sheet sample.
Output circuit terminal impedance.
Longitudinal Balance.
Recording of test data. - SS033400034
Performing the tests. - SS033400035
Output circuit.
Figure 1-16. Longitudinal balance data sheet, sample.
Phase Jitter.
Test arrangements.
Figure 1-17. Typical phase jitter test arrangement, block diagram
Figure 1-18. Effect of phase jitter on lissajous pattern oscilloscope display.
Figure 1-19. Phase jitter data sheet, sample.
Performing the test. - SS033400043
Study Exercises - SS033400044
Study Exercises (Cont) - SS033400045
Study Exercises (Cont) - SS033400046
Study Exercises (Cont) - SS033400047
Study Exercises (Cont) - SS033400048
Study Exercises (Cont) - SS033400049
Study Exercises (Cont) - SS033400050
Study Exercises (Cont) - SS033400051
Study Exercises (Cont) - SS033400052
Lesson 2. Equalizing Procedures
Envelope-Delay Distortion.
Definitions.
Figure 2-1. Envelope-delay-distortion test, block diagram.
Performing the test, end-to-end method.
Calculating relative delays.
Calibration and adjustment of controls.
Figure 2-2. Envelope-delay-distortion data sheet, sample.
Preparation.
Amplitude-Frequency Response.
Test arrangement. - SS033400063
Figure 2-3. Frequency response test, block diagram.
Performing the test. - SS033400065
Figure 2-4. Frequency response data sheet, sample.
Equalizing.
Equalizer used.
Correcting delay distortion.
Figure 2-6. Typical delay characteristics of individual sections.
Correcting amplitude distortion.
Study Exercises - SS033400072
Study Exercises (Cont) - SS033400073
Study Exercises (Cont) - SS033400074
Figure 2-7. Graph of delay limits in parameter S3.
Study Exercises (Cont) - SS033400076
Study Exercises (Cont) - SS033400077
Figure 2-8. Graph of loss variation in parameter S3.
Study Exercises (Cont) - SS033400079
Study Exercises (Cont) - SS033400080
Study Exercises (Cont) - SS033400081
Lesson 3. Record Keeping
Record Filing System.
Practical value of records.
Figure 3-1. Circuit history file.
Equipment utilization records
Figure 3-2. Equipment utilization record, sample.
A nonformatted report
Numbering.
Quality Control.
Table I. Circuit Quality Control Test Schedule
Parameter information.
Figure 3-3. Circuit Parameter Test Report, Sample.
Table II. Index of Test Description
Table II. Index of Test Description (cont)
Study Exercises - SS033400096
Study Exercises (cont) - SS033400097
Study Exercises (cont) - SS033400098
Study Exercises (cont) - SS033400099
Study Exercises (cont) - SS033400100
Solution Sheet
Solution Sheet (Cont) - SS033400102
Solution Sheet (Cont) - SS033400103
Solution Sheet (Cont) - SS033400104
Solution Sheet (Cont) - SS033400105
Solution Sheet (Cont) - SS033400106
Telephone Circuit Conditioning

Western Governors University

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