a. When the signal at input A changes to +6 volts (H), diode CR1 is forward biased and +6
volts is developed across R1. The +6 volts at the top of R1 is felt at the base of Q1 and the forward bias
on the base-emitter function drives the transistor not only into conduction but also into saturation.
b. In saturation, the collector of Q1 drops to 0 volts (L) and this changes the R2-R3 voltage
divider. Q1 is in parallel with R3 and, in saturation, the low resistance of Q1 practically shorts out R3.
It's like closing a switch that applies ground to the junction of R2 and R3. The current path is from
ground, through the switch (Q1), and through R2 to the positive supply; R3 is bypassed.
c. The low at the R2-R3 function is applied to the base of Q2. With 0 volts on its base, Q2
stops conducting. When current in Q2 stops, its collector voltage rises to the level of the supply voltage
d. The high at the collector also appears at the output. Thus, with a high on input A, the output
of the circuit is a high. This fact is shown in line 2 of the truth table. The OR gate proves correct with a
second condition: one active input (H) causes an output (H). Expressed in binary, this is stated as a 1 in
causes a 1 out.
e. Assume now that input A returns it to low and input B rises to a high. What will happen?
(1) A high on input B forward biases CR 2 and the high is applied to the base of Q1. Except
for the diode used, the same action occurs as when input A received a high -; a high is applied to the
base of Q1.
(2) From this point on, the operation is the same as before. Q1 goes into saturation and
applies 0 volts to Q2. Q2 cuts off and the output is a high. Again a high in causes a high out. The third
line of the truth table shows this condition. In general, any high (binary 1) into an OR gate causes a high
(binary 1) out.
We have only one condition left to check through the schematic. What happens to the circuit if
more than one input is a high? If the rules for OR gates hold true, the output should still be a high as
indicated in line 4 of the truth table.
a. Having inputs A and B at +6 volts means that both CR1 and CR2 are forward biased.
Resistor R1 still drops 6 volts and the +6 volts at the top of R1 biases Q1 into conduction.
b. From here on its operation is the same. Saturation of Q1 drops its collector voltage to 0 and
this drives Q2 into cutoff.
c. With Q2 cut off, the output is a high and the fourth condition completes the proof of the OR
gate rule. We can now say that "any one or more high inputs causes a high output," or, "any 1 in causes
a 1 out."