(1) When neither input is active (low on inputs A and B), the 0 voltage forward biases both
diodes. Current flows from the inputs, (through resistor R1) to the +6 volt supply. The entire +6 volts
are dropped across the resistor and there is 0 voltage at the top of R1 - the output. Two lows in cause a
low out.
(2) When input A is low and input B is high, diode CR1 is forward biased. Current flows
from input A, through R1 to the +6 volt supply. This holds the output at 0 volts and also reserve biases
CR2 (negative anode, positive cathode).
(3) When input A is high but input B is low, diode CR2 is forward biased. This holds the
output at 0 volts and reserve biases CR1.
(4) When both inputs are high, the output rises to the +6 volt value of the supply voltage.
b. Based on the results in (1) through (4) above, the only way to get a high output is to have all
inputs high. In (1), (2), and (3) we proved that if any input is low, the output is low. Only (4) produced
a high output; when input A is a 1 and input B is a 1, then the output is a 1.
c. There is one possible exception in para 3a(4) above. If the voltage level at the inputs is less
than the supply voltage, the output will be equal to the lower one - the input voltage. This occurs
because anything less than +6 volts on any input forward biases the associated diode and causes it to
conduct. The voltage at the output, then, is always equal to the input voltage, unless the input is greater
than +6. Thus, a diode AND gate cannot restore signal levels. If voltage amplification is required, the
diode gate must be replaced by a transistorized circuit that performs as an AND gate.
4.
The negative logic diode AND gate in A, Figure 3-6, operates the same way as the positive gate
but, of course, it follows the rules of negative logic - only if all inputs are low (-6) is the output low (-6).
Any one high (0 volt) input to the negative logic AND gate caused a high output (0 volt).
5.
Increasing the advantages or capabilities of anything usually increases its complexity and the
AND gate is no exception. For example, the transistorized AND gate in A, Figure 3-7, is a positive
logic AND gate. Although it may seem complicated, its operation is relatively simple.
a. From the inputs to the base of the transistor Q1, the circuit operation is identical to the diode
AND gate; and, from Q1 to the output, is the same as the OR gate. (The negative logic counterpart to
this circuit uses a negative logic diode AND gate.)
b. The only way to get a high to the base of Q1 is to have two highs on the input. When this
condition exists, Q1 conducts and the 0 volts from its collector drives Q2 into cut-off. When Q2 is cut
off, the output rises to the +6-volt supply voltage. Any low on the input is felt at the base of Q1 and cuts
it off. The R2-R3 voltage divider then supplies a positive voltage to
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